The present invention relates to a buffer for interfacing a signal to a device and, in particular, to a buffer that is capable of interfacing between a TTL compatible output signal provided by a device operated with a five volt nominal supply voltage and a device suited for operation with a supply voltage that is substantially less than five volts, e.g. 2.5 volts.
A buffer is used in digital logic assemblies to provide a separation in impedance between logic elements. Buffers are frequently used in combination with logic elements as part of an integrated circuit (IC). These integrated circuits make use of an input buffer for receiving logic signals from other assemblies and output buffers for transmitting logic signals to other logic assemblies.
Input buffers that are part of an integrated circuit are frequently used to interface relatively low logic impedance elements with logic elements that have relatively high impedance. These low impedance elements are often output buffers that are capable of driving loads that have relatively low input impedance. In contrast, the high impedance elements are frequently logic elements that have high input impedance and are part of the integrated circuit. These input buffers may also provide additional features such as electrostatic discharge protection for preventing relatively large voltages on the logic inputs from damaging the integrated circuit. In addition, input buffers are frequently capable of interpreting an electrically unconnected input or "floating" input to the integrated circuit as a predefined logic state. For example, TTL input buffers frequently make use of a pull down resistor so that a floating input is interpreted as a logic low state.
When interfacing between digital logic assemblies of different families, it is often necessary that a level shifter or translator circuit be used. Each of these families of integrated circuits, such as complementary-metal-oxide-semiconductor (CMOS), transistor-transistor logic (TTL) and emitter coupled logic (ECL) have characteristic parameters for logic high and logic low states. Therefore, the translator or level shifter must be capable of accepting the voltage or current levels from one logic family and providing the appropriate voltage and current levels for the second integrated circuit family for which the translator is providing an interface.
FIG. 1 shows a prior art input buffer 10 that operates with a five volt nominal supply voltage. Input buffer 10 includes an input terminal 12 for receiving a TTL compatible signal from a device operating with a five-volt nominal supply voltage. Input buffer 10 further includes a pair of output terminals 14 and 16 for providing a differential current mode logic (CML) signal for a device operating at a five volt nominal supply. Signals present at output terminals 16 and 14 represent the positive or true output signal and the negative or complement output signal, respectively. The positive side of the supply voltage is connected to a terminal 18 and the negative side of the supply voltage is connected to a terminal 20.
Input buffer 10 includes a switch control transistor 22 that receives a signal at the input terminal 12 and provides a control signal for operating a current switch circuit. The current switch circuit includes a pair of transistors 24 and 26 that are connected in a common emitter configuration to a current source transistor 28. Each of transistors 24, 26 and current source transistor 28 have an emitter, base and collector.
A constant polarity voltage bias is applied between the base and emitter of current source transistor 28. The current source transistor 28 is biased by resistor 30, diode 32, transistor 34 and resistor 36 each connected in series between the positive terminal 18 and the negative terminal 20. Transistor 34 has a base and a collector that are electrically connected together to form a PN junction between the collector and an emitter.
The bias voltage applied to the base of current source transistor 28 is equal to a forward bias voltage drop across the PN junction of transistor 34 plus a voltage drop across resistor 36 resulting from a current passing therethrough. Resistor 36 is selected such that the bias current that passes between the positive terminal 18 and negative terminal 20 through resistor 36 causes a voltage drop of approximately 700 millivolts to occur across the resistor 36. Therefore, the bias voltage provided between the base of transistor 28 and the negative terminal 20 is approximately equal to 700 millivolts plus the 700 millivolt forward bias voltage drop across transistor 34, or 1.4 volts. The bias voltage applied to the base of transistor 28 is constant as long as the voltage between terminals 18 and 20 is constant.
This bias voltage applied to the base of current source transistor 28 forward biases the base-emitter junction so that current is conducted between the collector and the emitter of the current source transistor 28. In this manner, current source transistor 28 conducts or sinks current provided by each of the emitters of transistors 24 and 26.
Transistor 26 has a bias voltage applied between its base and the negative terminal 20 that is equal to the sum of the bias voltage applied to the base of the current source transistor 28 plus the forward bias voltage drop across diode 32. The forward bias voltage drop across diode 32 is approximately 700 millivolts. Therefore, the bias voltage applied to transistor 26 is approximately equal to 2.1 volts or the forward bias voltage drop of three PN junction diodes connected in series. The bias voltages applied to transistor 26 are relatively constant as long as the supply voltage applied between terminals 18 and 20 is constant. The bias voltage applied to transistor 26 sets the voltage threshold level at which transistor 26 transitions from a conducting state where current is conducted between the collector and the emitter and a non-conducting state where current is substantially prevented from passing between the collector and the emitter. Transistor 26 is in the conducting state when the voltage between the base and emitter is sufficiently large so that a PN junction between the base and emitter is forward biased. Conversely, transistor 26 is in the non-conducting state when the PN junction between the base and the emitter, respectively, is reverse biased.
Transistor 24 has a conducting state and a non-conducting state similar to transistor 26. Transistor 24 is in a conducting state if a PN junction between the base and emitter is forward biased and in a non-conducting state if the PN junction is reverse biased.
Transistors 24 and 26 together form a symmetrical current switch for providing current to the current source transistor 28. The base of transistor 24 is connected to the emitter of the switch control transistor 22. As the voltage at the emitter of the switch control transistor 22 varies between relatively high voltages and relatively low voltages, the operation of transistor 24 varies between conducting and non-conducting states. If the voltage provided by switch control transistor 22 to the base of transistor 24 is sufficiently large, then transistor 24 is in the conducting state. If the voltage applied to the base of transistor 24 by switch control transistor 22 is not large enough so that transistor 24 is in the conducting state, then only transistor 26 will be in the conducting state.
Because transistors 24 and 26 are connected in a common emitter configuration, voltages applied to the base of transistor 24 also affect the operation of transistor 26. If the voltage provided to the base of transistor 24 is sufficiently large, the voltage at the common emitter of transistors 24 and 26 rises so that transistor 26 is no longer forward biased and is therefore not in the conducting state.
The current conducted by both transistors 24 and 26 will have an inverse relationship that results from the common emitter configuration. Therefore, as the current conducted between the collector and emitter of transistor 24 increases, the current conducted between the collector and the emitter of transistor 26 decreases. Conversely, as the current conducted between the collector and the emitter of transistor 24 decreases, the current conducted between the collector and emitter of transistor 26 increases. The current that enters the collector of current source transistor 28 is equal to the sum of the currents provided by the emitter of transistors 24 and 26.
Transistor 24 and transistor 26 are each connected to separate collector circuits. The current provided by the emitter of transistor 24 is substantially the same as the current passing through a resistor 38 that is electrically connected between the positive terminal 18 and the collector of transistor 24 except for a small current entering the base of transistor 24. Similarly, the current provided by the emitter of transistor 26 is substantially the same as the current passing through resistor 40 that is electrically connected between the positive terminal 18 and the collector of transistor 26, except for a small current entering the base of transistor 26.
The voltage at the output terminals 14 and 16 are related to current entering the collector of transistors 24 and 26, respectively. The output terminals 14 and 16 each has an output voltage present that is equal to the voltage at the positive supply terminal 18 minus the voltage drop across the resistors 38 and 40, respectively, that are electrically connected between the positive supply 18 and the output terminals. Therefore, the voltage at output terminal 14 relative to terminal 20 is equal to the voltage at positive terminal 18 minus the product of the resistance of resistor 38, in ohms, and the current entering the collector of transistor 24. Similarly, the voltage at output terminal 16 is equal the voltage at the positive terminal 18 minus the product of the resistance of resistor 40, in ohms, and the current entering the collector of transistor 26. If transistors 24 and 26 are matched and resistors 38 and 40 are identical, then the voltage swing at output terminals 14 and 16 will be the same.
The switch control transistor 22 is biased through resistor 46 that is connected between an emitter and the positive terminal 18. The bias on switch control transistor 22 allows the voltage at the emitter to track the voltage at the base. The emitter of switch control transistor 22 is level-shifted from the voltage at the base by the forward bias voltage drop of the emitter-base junction. The switch control transistor 22 selects the source of current provided to current source transistor 28 based on the signal at input terminal 12. If the voltage between the input terminal 12 and the negative terminal 20 is in a logic low state, then the emitter-base are forward biased and switch control transistor 22 is in a conducting state. When in the conducting state, current passes from the positive terminal through resistor 46 causing a voltage drop across resistor 46 thereby reducing the voltage at the base of transistor 24. If the voltage at the base becomes sufficiently reduced, transistor 24 becomes non-conducting.
Alternatively, resistor 46 may be replaced by a PNP transistor having an emitter connected to the positive terminal 18, a collector connected to the emitter of transistor 22 and a base connected to a bias or current source. In this arrangement, the PNP transistor provides bias current to transistor 22 as well as base current to transistor 24 in a manner similar to resistor 46.
If the voltage between the input terminal 12 and the negative terminal 20 is in a logic high state, then the emitter-base are reverse biased and switch control transistor 22 is in a non-conducting state. When in the non-conducting state, very little current, if any, flows through resistor 46 thereby causing the voltage at the base of transistor 24 to be pulled up to or nearly equal to the positive terminal 18 voltage. When the voltage at the base of transistor 24 becomes sufficiently large, the transistor 24 will be in the conducting state. As will be discussed, a clamping transistor 48 prevents the voltage at the base from becoming too large thereby preventing the saturation of transistor 24.
A clamping transistor 48, having a base, an emitter and a collector, is provided to prevent the transistor 24 from saturating and thereby providing a non-symmetrical signal at output terminals 14 and 16. The clamping transistor 48 is connected so that the emitter is connected to the base of transistor 22 and the collector connected to the negative terminal 20. The clamping transistor prevents saturation of the transistor 24 by conducting current between the collector and emitter thereby limiting the voltage at the base of transistor 24. The clamping threshold or voltage at the base of transistor 24 for which the clamping transistor 48 conducts is set by the voltage at the base of clamping transistor 48. If the voltage at the emitter of transistor 48 is sufficiently large relative to the voltage drop across the series combination of diode 32, diode 34 and the voltage across resistor 36 due to the current flowing therethrough, then the emitter-base becomes forward biased and transistor 48 conducts limiting or clamping the positive voltage excursion at the base of transistor 24.
A degeneration resistor 42 is connected between the emitter of current source transistor 28 and the negative terminal 20. Emitter degeneration resistors are known and are used in common emitter amplifiers to provide feedback increasing voltage stability as well as increasing both the input impedance and output impedance. The emitter degeneration resistor 42 also increases the range of voltages supplied at input terminal 12 over which the voltage at output terminals 14 and 16 behaves in a linear fashion. Finally, the degeneration resistor 42 sets the transition time for the voltage swing at the output terminals 14 and 16 by setting the current passing through current source transistor 28.
Resistor 52 is a pull-down resistor for pulling the voltage at the base of switching transistor 22 low or toward the voltage of the negative terminal 20 if the input terminal 12 is in a floating state. An input resistor 44 is connected between input terminal 12 and the switch control transistor 22 for limiting large in-rush currents such as those caused by an electrostatic discharge. Epitaxial connections 60 and 62 are made between the positive terminal 18 and each of resistors 52 and 44.
Buffer 10 requires that the supply voltage be sufficiently large so that transistor 24 is in the conducting state when a logic high signal is provided to input terminal 12. To ensure transistor 24 conducts in this condition, the supply voltage must be greater than the bias voltage applied to the base of transistor 48, 2.1 volts, plus the forward bias voltage drop of the PN junction between the base and emitter of transistor 48, 0.7 volts. Therefore, the supply must be greater than 2.8 volts to ensure transistor 24 achieves the proper voltage swing and that clamping transistor 48 is in the conducting mode when transistor 24 is conducting maximum current. However, because the forward bias voltage drop for both the base emitter junctions of transistors 48 and 34 and the diode 32 have large temperature coefficients under worst case temperature conditions, the minimum supply voltage must be much greater than 2.8 volts. Under worst case temperature conditions, the voltage drop across the emitter base junctions for transistors 48 and 34 and across diode 32 is approximately 0.85 volts each. Therefore, under worst case temperature conditions, the minimum supply voltage is approximately 3.25 volts. Therefore, buffer 10 does not readily lend itself to low supply voltage operation because an adequate voltage swing at the base of transistor 24 cannot be achieved at low supply voltages.
There is a present need for input buffers for integrated circuits of one logic family to interface with logic elements of another family that are capable of operation with a low supply voltage. These input buffers should be reliable, able to allow the voltage at the input terminal to be grater than the supply voltage and provide fast transition times between states.